Modern hardware devices that include a processor and one or more peripheral devices often make use of interrupts. Interrupts provide a useful way of sharing processor time among various software processes and hardware. Often events arise in peripheral devices that occur intermittently but may need to be handled quickly. Rather than wasting processor time by periodically polling a peripheral device to ascertain if an event that needs handling has occurred, a processor may perform other tasks and have the peripheral device signal when an event that needs to be handled occurs, by way of an interrupt request.
An interrupt request thus asynchronously signals a processor that requires some processor service is required. Typically each interrupt has an associated piece of code called an interrupt service routine (ISR). Upon receiving an interrupt request signal the processor identifies and executes the ISR associated with the received interrupt request.
To do so, the processor typically determines the source of the interrupt, saves the current state of the processor, and executes the remainder of the ISR. Data in the processor's registers, representative of the current state, are stored in a memory such as a stack before and later retrieved after the ISR is completed. Clearly, executing an ISR requires processor overhead.
Multiple interrupt requests require a mechanism to handle each interrupt. Two or more interrupts requests may also be received simultaneously. Moreover, a new interrupt may be received by the processor while an earlier interrupt is being handled. Thus, priorities are often assigned to different types of interrupts and higher priority interrupts may interrupt lower priority ones, and are thus serviced prior to lower priority ones. If an interrupt of a higher priority is received while an ISR associated with a lower priority interrupt is being executed, the ISR of higher priority interrupt commences execution immediately. After the higher priority ISR is completed, the lower priority ISR is resumed.
Although interrupts provide a useful way to share processing time efficiently, some peripheral devices may interrupt the processor too frequently. This often leads to system performance degradation resulting from overhead associated executing associate ISRs.
Of course, other software processes executing on the processor must compete with ISRs for processor time. Excessive generation of interrupts by a poorly designed peripheral device, or a poorly written ISR that takes too long to complete, limits the amount of time the processor devotes to executing other applications, which in turn leads to degradation of overall performance.
Accordingly, there is a need for a flexible and efficient interrupt generation and handling technique that may reduce the impact of excessive interrupts on system performance.